The aim of this project is to design a 5-stage pipelined MIPS processor, using Verilog HDL. The 5 stages being used are Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory (MEM) and Write Back (WB). The instruction set being used is of 32-bits. The various modules being used are Instruction Memory, Data Memory, ALU, Registers etc. I also have implemented a Forwarding Unit and a hazard detection unit for the detection of Data hazards. The main goal is to do the complete ASIC flow (RTL to GDS II), using Synopsys design tools. VCS is used for simulation, Synopsys DC Compiler for Synthesis (timing and area are optimized in this step) and Synopsys IC Compiler for Clock tree Synthesis and Place and Route. This report focuses upon, basics of RISC and CISC, MIPS Processor, Hazard detection in MIPS processor and also the simulation and synthesis based results and deductions.
- Date
- 2014-01-16
- Resource Type
- Creator
- Advisor
- Committee Member
- Campus
- Department
- Publisher
- Degree Level
- Masters
- Degree Name
- M.S.
- Subjects
- Date Copyright
- 2013
- Date Submitted
- 2013-12
- Date Accessioned
- 2014-01-16T17:59:24Z
- Handle
- Language
- Statement of Responsibility
- by Abhirup Jannu
- Notes
- Includes bibliographical references (page 42)
- California State University, Northridge. Department of Electrical and Computer Engineering.
