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D-type flip-flops
4-Bit D-type Registers with 3-State Outputs
Data sheet
- document-pdfAcrobat 4-Bit D-Type Registers With 3-State Outputs datasheet (Rev. A)
SN74LS173A
Product details
- 3-State Outputs Interface Directly With System Bus
- Gated Output-Control LInes for Enabling or Disabling the Outputs
- Fully Independent Clock Virtually Eliminates Restrictions for Operating in One of Two Modes:
- Parallel Load
- Do Nothing (Hold)
- For Application as Bus Buffer Registers
- Package Options Include Plastic Small-Outline (D) Packages, Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) DIPs
- 3-State Outputs Interface Directly With System Bus
- Gated Output-Control LInes for Enabling or Disabling the Outputs
- Fully Independent Clock Virtually Eliminates Restrictions for Operating in One of Two Modes:
- Parallel Load
- Do Nothing (Hold)
- For Application as Bus Buffer Registers
- Package Options Include Plastic Small-Outline (D) Packages, Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) DIPs
The '173 and 'LS173A 4-bit registers include D-type flip-flops featuring totem-pole 3-state outputs capable of driving highly capacitive
or relatively low-impedance loads. The high-impedance third state and increased high-logic-level drive provide these flip-flops with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. Up to 128 of the SN74173 or SN74LS173A outputs can be connected to a common bus and still drive two Series 54/74 or 54LS/74LS TTL normalized loads, respectively. Similarly, up to 49 of the SN54173 or SN54LS173A outputs can be connected to a common bus and drive one additional Series 54/74 or 54LS/74LS TTL normalized load, respectively. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels, the output control circuitry is designed so that the average output disable times are shorter than the average output enable times.
Gated enable inputs are provided on these devices for controlling the entry of data into the flip-flops. When both data-enable (G\1, G\2) inputs are low, data at the D inputs are loaded into their respective flip-flops on the next positive transition of the buffered clock input. Gate output-control (M, N) inputs also are provided. When both are low, the normal logic states (high or low levels) of the four outputs are available for driving the loads or bus lines. The outputs are disabled independently from the level of the clock by a high logic level at either output-control input. The outputs then present a high impedance and neither load nor drive the bus line. Detailed operation is given in the function table.
The SN54173 and SN54LS173A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74173 and SN74LS173A are characterized for operation from 0°C to 70°C.
The '173 and 'LS173A 4-bit registers include D-type flip-flops featuring totem-pole 3-state outputs capable of driving highly capacitive
or relatively low-impedance loads. The high-impedance third state and increased high-logic-level drive provide these flip-flops with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. Up to 128 of the SN74173 or SN74LS173A outputs can be connected to a common bus and still drive two Series 54/74 or 54LS/74LS TTL normalized loads, respectively. Similarly, up to 49 of the SN54173 or SN54LS173A outputs can be connected to a common bus and drive one additional Series 54/74 or 54LS/74LS TTL normalized load, respectively. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels, the output control circuitry is designed so that the average output disable times are shorter than the average output enable times.
Gated enable inputs are provided on these devices for controlling the entry of data into the flip-flops. When both data-enable (G\1, G\2) inputs are low, data at the D inputs are loaded into their respective flip-flops on the next positive transition of the buffered clock input. Gate output-control (M, N) inputs also are provided. When both are low, the normal logic states (high or low levels) of the four outputs are available for driving the loads or bus lines. The outputs are disabled independently from the level of the clock by a high logic level at either output-control input. The outputs then present a high impedance and neither load nor drive the bus line. Detailed operation is given in the function table.
The SN54173 and SN54LS173A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74173 and SN74LS173A are characterized for operation from 0°C to 70°C.
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Technical documentation
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View all 12Type | Title | Date | ||
---|---|---|---|---|
* | Data sheet | 4-Bit D-Type Registers With 3-State Outputs datasheet (Rev. A) | 01 Jun 1999 | |
White paper | Understanding Functional Safety FIT Base Failure Rate Estimates per IEC 62380 and SN 29500 (Rev. A) | PDF | HTML | 30 Apr 2024 | |
Application note | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | 15 Dec 2022 | |
Selection guide | Logic Guide (Rev. AB) | 12 Jun 2017 | ||
Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 02 Dec 2015 | ||
User guide | LOGIC Pocket Data Book (Rev. B) | 16 Jan 2007 | ||
Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 08 Jul 2004 | ||
Application note | TI IBIS File Creation, Validation, and Distribution Processes | 29 Aug 2002 | ||
Application note | Designing With Logic (Rev. C) | 01 Jun 1997 | ||
Application note | Designing with the SN54/74LS123 (Rev. A) | 01 Mar 1997 | ||
Application note | Input and Output Characteristics of Digital Integrated Circuits | 01 Oct 1996 | ||
Application note | Live Insertion | 01 Oct 1996 |
Design & development
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Evaluation board
14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages
The 14-24-LOGIC-EVM evaluation module(EVM)is designed to support any logic device that is in a 14-pin to 24-pinD, DW, DB, NS, PW, DYYor DGV package,
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Package | Pins | CAD symbols, footprints & 3D models |
---|---|---|
PDIP (N) | 16 | Ultra Librarian |
SOIC (D) | 16 | Ultra Librarian |
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